The PC/104–MVB Card connects a PC via the PC/104 standard bus with a “Multifunctional Vehicle Bus (MVB) – IEC61375” system.
The interface between PC/104 and MVBC is implemented in a Xilinx Spartan-XL FPGA. Additionally the FPGA contains the control and status logic for the Traffic Memory access. The address range for accesing the MVBC and “Traffic Memory“ is configurable using a register in the PC-AT IO space.
Additionally the FPGA design contains support logic for:
– Memory models for class 2,3,4 [MVBC]
– Interrupt controller for both MVBC interrupt sources
– Busrequest logic for MVBC register access
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